Burst mode clock and data recovery circuit and method
US8243869B2 · kind B2 · utility
6Cited by
6References
26Claims
0Family size
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Key dates
| Filing date | Nov 28, 2006 |
| Grant date | Aug 14, 2012 |
| Priority date | — |
| Expiry date | Aug 18, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0025
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Burst mode clock and data recovery (BCDR) circuit and method capable of fast data recovery of passive optical network (PON) traffic. An over-sampled data stream is generated from an input burst data signal and a phase interpolator generates sampling clock signals using a reference clock and phase information. A phase estimation unit (PEU) determines a phase error in the over-sampled data streams; and a phase retrieval unit sets the phase interpolator with the respective phase information of the input burst data signal prior to reception of the input burst data signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.