SSD with distributed processors
US8244961B2 · kind B2 · utility
9Cited by
0References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 19, 2009 |
| Grant date | Aug 14, 2012 |
| Priority date | — |
| Expiry date | Oct 4, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5641
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a system includes a serial data bus, a plurality of processors of a first type, and a processor of a second type. The serial data bus is configured to be coupled to a corresponding serial data bus of a host device. Each of the plurality of processors of the first type is coupled to a respective flash memory device. The processor of the second type is configured to manage the access that the plurality of the processors of the first type have to the serial data bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.