Memory access device including multiple processors
US8244987B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 2, 2009 |
| Grant date | Aug 14, 2012 |
| Priority date | — |
| Expiry date | Nov 16, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4234
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provided is a memory access device including multiple processors accessing a specific memory. The memory access device includes first and second processors, first and second transaction controllers, a memory access switch, and a memory controller. The first and second transaction controllers are connected respectively to the first and second processors. The memory access switch is connected to the first and second transaction controllers. The memory controller is connected to the memory access switch to control a memory device. Herein, if the first and second processors simultaneously access the memory device, the second processor stores an address or data in the second transaction controller while the first processor is accessing the memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.