ESD protection device with increased holding voltage during normal operation
US8247839B2 · kind B2 · utility
6Cited by
10References
24Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 9, 2009 |
| Grant date | Aug 21, 2012 |
| Priority date | — |
| Expiry date | Oct 17, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/713
Abstract
An ESD protection circuit including an SCR having at least one PNP transistor and at least one NPN transistor such that at least one of the PNP transistor and the NPN transistor having an additional second collector. The circuit further including at least one control circuit coupled to the at least one second collector to control holding voltage of the SCR.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.