Track and hold architecture with tunable bandwidth
US8248282B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 17, 2010 |
| Grant date | Aug 21, 2012 |
| Priority date | — |
| Expiry date | Dec 22, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/1215
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
To date, bandwidth mismatch within time-interleaved (TI) analog-to-digital converters (ADCs) has been largely ignored because compensation for bandwidth mismatch is performed by digital post-processing, namely finite impulse response filters. However, the lag from digital post-processing is prohibitive in high speed systems, indicating a need for blind mismatch compensation. Even with blind bandwidth mismatch estimation, though, adjustment of the filter characteristics of track-and-hold (T/H) circuits within the TI ADCs can be difficult. Here, a T/H circuit architecture is provided that uses variations of the gate voltage of a sampling switch (which varies the “on” resistance of the sampling switch) to change the bandwidth of the T/H circuits so as to precisely match the bandwidths.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.