Massively parallel supercomputer
US8250133B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 26, 2009 |
| Grant date | Aug 21, 2012 |
| Priority date | — |
| Expiry date | Feb 13, 2030 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02B30/70
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A novel massively parallel supercomputer of hundreds of teraOPS-scale includes node architectures based upon System- On-a-Chip technology, i.e., each processing node comprises a single Application Specific Integrated Circuit (ASIC). Within each ASIC node is a plurality of processing elements each of which consists of a central processing unit (CPU) and plurality of floating point processors to enable optimal balance of computational performance, packaging density, low cost, and power and cooling requirements. The plurality of processors within a single node individually or simultaneously work on any combination of computation or communication as required by the particular algorithm being solved. The system-on-a-chip ASIC nodes are interconnected by multiple independent networks that optimally maximizes packet communications throughput and minimizes latency. The multiple networks include three high-speed networks for parallel algorithm message passing including a Torus, Global Tree, and a Global Asynchronous network that provides global barrier and notification functions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.