Techniques for balancing system I/O load
US8250257B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 8, 2010 |
| Grant date | Aug 21, 2012 |
| Priority date | — |
| Expiry date | Dec 8, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2206/1012
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Described are techniques for performing I/O operations. A graph is received including a plurality of nodes and edges. The graph includes a first level with a root node and one or more other levels of nodes. Each edge has a value indicating an I/O load metric. A thread associated with a first node determines whether to perform a background I/O operation directed to a first device and having a first priority. The first priority is compared to a first value of an I/O load metric. The first value is determined in accordance with criteria including a maximum usage of an I/O buffer of the first device and priorities of other I/O operations directed to the first device. If it is determined that the background I/O operation is to be performed, the background I/O operation is forwarded for processing on an I/O path having a corresponding path in the graph.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.