Mechanisms for reducing DRAM power consumption
US8250298B2 · kind B2 · utility
4Cited by
7References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 27, 2010 |
| Grant date | Aug 21, 2012 |
| Priority date | — |
| Expiry date | Feb 11, 2031 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Mechanisms are provided for inhibiting precharging of memory cells of a dynamic random access memory (DRAM) structure. The mechanisms receive a command for accessing memory cells of the DRAM structure. The mechanisms further determine, based on the command, if precharging the memory cells following accessing the memory cells is to be inhibited. Moreover, the mechanisms send, in response to the determination indicating that precharging the memory cells is to be inhibited, a command to blocking logic of the DRAM structure to block precharging of the memory cells following accessing the memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.