Compiling code for parallel processing architectures based on control flow
US8250555B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 7, 2008 |
| Grant date | Aug 21, 2012 |
| Priority date | — |
| Expiry date | Jun 2, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0837
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system comprises a plurality of computation units interconnected by an interconnection network. A method for configuring the system comprises forming subsets of instructions corresponding to different portions of a program, the subsets of instructions being related according to a control flow graph; for each of a first subset of branches in the control flow graph, scheduling a value of an associated branch condition to be broadcast to multiple computation units; for each of a second subset of branches in the control flow graph, representing each instruction dependent on an associated branch condition as a predicated instruction that includes a predicate for computing the associated branch condition; assigning each subset of instructions to one of the computation units for execution on the assigned computation unit; and converting at least some of the predicated instructions in a subset of instructions assigned to a given computation unit into unpredicated instructions that depend on a branch local to the given computation unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.