Thin film transistor array panel and manufacturing method thereof
US8252626B2 · kind B2 · utility
12Cited by
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9Claims
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Key dates
| Filing date | Jun 21, 2010 |
| Grant date | Aug 28, 2012 |
| Priority date | — |
| Expiry date | Apr 15, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K71/621
Abstract
A manufacturing method for a thin film transistor array panel including forming a gate electrode, forming an insulating layer on the gate electrode, sequentially forming a lower conducting layer and a upper conducting layer on the insulating layer, etching the upper conducting layer to form a first source electrode and a first drain electrode, etching the lower conducting layer to form the second source electrode and the second drain electrode, over-etching the second source electrode and the second drain electrode, and forming an organic semiconductor between the second source electrode and the second drain electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.