Sealed semiconductor device
US8253175B2 · kind B2 · utility
Inventors
Key dates
| Filing date | Jan 18, 2010 |
| Grant date | Aug 28, 2012 |
| Priority date | — |
| Expiry date | Oct 3, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01S2301/176
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A sealed semiconductor device having reduced delamination of the sealing layer in high temperature, high humidity conditions is disclosed. The semiconductor device includes a substrate and a stack of device layers on the substrate sealed with a sealing layer. The upper surface of a street area of the substrate is oxidized so that the oxidized region extends under the sealing layer. The presence of the oxidized region of the upper surface of the substrate helps reduce the delamination, because the oxidized surface does not react with water to the same extent as a non-oxidized surface. The semiconductor devices remain sealed after dicing through the street area because the oxidized surface does not delaminate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.