Circuits and methods for level shifting a signal
US8253441B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 22, 2011 |
| Grant date | Aug 28, 2012 |
| Priority date | — |
| Expiry date | Mar 22, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/356121
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In one embodiment, the present disclosure includes a level shift circuit. The level shift circuit includes a clocked latch to receive a digital data signal and a complement of the digital data signal. Outputs of the clocked latch are coupled to inputs of a second latch through capacitors. The clocked latch is powered by first and second power supply voltages that are different than third and fourth power supply voltages used for powering the second latch. Latch output signals from the second latch have high and low voltage values at the third and fourth power supply voltages. In one embodiment, transistors in circuitry driven by the level shift circuit may receive output signals from the level shift circuit that have high and low voltage values within a safe operating range of the transistor receiving the output signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.