High impedance bias network
US8253471B2 · kind B2 · utility
0Cited by
9References
20Claims
0Family size
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Key dates
| Filing date | Oct 6, 2010 |
| Grant date | Aug 28, 2012 |
| Priority date | — |
| Expiry date | Feb 26, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04R2410/00
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
This document discusses, among other things, a system and method for offsetting reverse-bias leakage of a high impedance bias network. In an example, an apparatus includes an anti-parallel diode pair coupled between a signal node and a common-mode node. The anti-parallel diode pair can include a first diode and a second diode coupled to the first diode. A third diode can be coupled between a supply node and the signal node, and the third diode can be sized to compensate for a parasitic diode junction of the anti-parallel diode pair.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.