Semiconductor memory device
US8254160B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 21, 2010 |
| Grant date | Aug 28, 2012 |
| Priority date | — |
| Expiry date | Mar 25, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/75
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to one embodiment, a semiconductor memory device includes: word lines; bit lines; an insulating film; an interlayer insulating film; and a resistance varying material. The word lines, the bit lines and the insulating film configure a field-effect transistor at each of the intersections of the word lines and the bit lines. The field-effect transistor has one of the word lines as a control electrode and one of the bit lines as a channel region. The field-effect transistor and the resistance varying material configure a memory cell having the field-effect transistor and the resistance varying material connected in parallel. Each of the bit lines includes a first surface opposing the word lines, and a second surface on an opposite side to the first surface. The resistance varying material is disposed in contact with the second surface and has a portion thereof in contact with the interlayer insulating film.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.