Joint encoding of logical pages in multi-page memory architecture
US8254167B2 · kind B2 · utility
15Cited by
6References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 17, 2010 |
| Grant date | Aug 28, 2012 |
| Priority date | — |
| Expiry date | Feb 12, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Multiple logical pages are jointly encoded into a single code word and are stored in the same physical page of a solid state non-volatile memory (NVM) device having multi-level memory cells. A first logical page of the multiple logical pages is stored in the memory device as first bits of the multi-level memory cells while a second logical page of the multiple logical pages is temporarily cached. After the first logical page is stored as the first bits of the memory cell, the second logical page is stored as second bits of the memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.