Nonvolatile semiconductor memory device and write method for the same
US8254168B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 22, 2010 |
| Grant date | Aug 28, 2012 |
| Priority date | — |
| Expiry date | Dec 17, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5621
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to one embodiment, a semiconductor device includes memory cells, bit lines, a write circuit, and sense amplifiers. The bit lines are connected to the memory cells. The sense amplifiers are configured to bias the bit line to which the selected memory cell is connected, to a first voltage until the threshold of the selected memory cell reaches the value of a first write state. Then, when the threshold of the selected memory cell reaches the value of the first write state, the bit line is biased to a second voltage higher than the first voltage. When the threshold of the selected memory cell reaches the value of a second write state, the bit line is continuously biased to a third voltage higher than the second voltage. Bit lines connected to unselected memory cells corresponding to the memory cells other than the selected one are biased to the third voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.