Wear leveling non-volatile semiconductor memory based on erase times and program times
US8254172B1 · kind B1 · utility
204Cited by
1References
12Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 30, 2009 |
| Grant date | Aug 28, 2012 |
| Priority date | — |
| Expiry date | Sep 12, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/349
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-volatile semiconductor memory is disclosed comprising a memory device including a plurality of memory segments. A program command is issued to the memory device to program a memory segment, and a program time required to execute the program command is saved. An erase command is issued to the memory device to erase the memory segment, and an erase time required to execute the erase command is saved. A wear leveling algorithm is executed for the memory segment in response to the program time and the erase time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.