Hardware abstraction layer
US8254285B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 28, 2005 |
| Grant date | Aug 28, 2012 |
| Priority date | — |
| Expiry date | May 27, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/70
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Switching and routing functions may be provided in a data plane of a network switch by having all functions and algorithms needed to handle all related interface, logical and physical, under one interface manager to keep track of bindings between virtual interfaces and logical interfaces, as well as maintain the statuses of ports that belong to the virtual interface and the actual logical ports. When the actual interface goes down, the virtual interface may go down along with it. The bindings may also include definitions. All of these bindings may be located in a single routing information base (RIB) database, eliminating the need for multiple bindings to be kept in various places. Furthermore, a hardware abstraction layer in the control plane can also then be mirrored in the data plane, eliminating the need for the customer to create a layer performing the same tasks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.