Compact load balanced switching structures for packet based communication networks
US8254390B2 · kind B2 · utility
4Cited by
5References
6Claims
0Family size
Assignee
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Key dates
| Filing date | Dec 19, 2005 |
| Grant date | Aug 28, 2012 |
| Priority date | — |
| Expiry date | Sep 19, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/90
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A switching node is disclosed for the routing of packetized data employing a multi-stage packet based routing fabric combined with a plurality of memory switches employing memory queues. The switching node allowing reduced throughput delays, dynamic provisioning of bandwidth and packet prioritization.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.