Partition transparent correctable error handling in a logically partitioned computer system
US8255639B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 6, 2008 |
| Grant date | Aug 28, 2012 |
| Priority date | — |
| Expiry date | Dec 10, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for transparently handling recurring correctable errors to prevent costly system shutdowns for correctable memory errors or system failures from uncorrectable memory errors. When a high number of correctable errors are detected for a given memory location, the hypervisor moves the data associated with the memory location to an alternate physical memory location transparently to the partition such that the partition has no knowledge that the physical memory actualizing the memory location has been changed. Similarly, the hypervisor can move direct memory access (DMA) memory locations using an I/O translation table.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.