Network communications processor architecture with memory load balancing
US8255644B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 18, 2010 |
| Grant date | Aug 28, 2012 |
| Priority date | — |
| Expiry date | Jan 27, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/506
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Described embodiments provide a memory system including a plurality of addressable memory arrays. Data in the arrays is accessed by receiving a logical address of data in the addressable memory array and computing a hash value based on at least a part of the logical address. One of the addressable memory arrays is selected based on the hash value. Data in the selected addressable memory array is accessed using a physical address based on at least part of the logical address not used to compute the hash value. The hash value is generated by a hash function to provide essentially random selection of each of the addressable memory arrays.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.