Atomic hash instruction
US8255703B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 20, 2011 |
| Grant date | Aug 28, 2012 |
| Priority date | — |
| Expiry date | Jan 20, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2209/60
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for performing a hash operation, including providing an atomic hash instruction that directs a microprocessor to perform a the hash operation and to indicate whether the hash operation has been interrupted by an interrupting event; translating the atomic hash instruction into first and second micro instructions; via a hash unit, first executing the first micro instructions to accomplish the hash operation according to the hash mode; and via an integer unit, second executing the second micro instructions in parallel with the first executing to test a bit in a flags register, to update text pointer registers, and to process interrupts during execution of the hash operation. The atomic hash instruction has an opcode field, configured to prescribe the hash operation, and a hash mode field, configured to prescribe that the microprocessor accomplish the hash operation according to a one of a plurality of hash modes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.