Multi-level cell memory device and method thereof
US8255770B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 9, 2011 |
| Grant date | Aug 28, 2012 |
| Priority date | — |
| Expiry date | May 9, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A Multi-Level Cell (MLC) memory device and method thereof are provided. The example MLC memory device may be configured to perform data operations, and may include an MLC memory cell, a first coding device performing a first coding function, the first coding function being one of an encoding function and a decoding function, a second coding device performing a second coding function, the second coding function being one of an encoding function and a decoding function and a signal module configured to perform at least one of instructing the MLC memory cell to store data output by the second coding device if the first and second coding functions are encoding functions, and generating a demapped bit stream based on data retrieved from the MLC memory cell if the first and second coding functions are decoding functions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.