Scalable VLIW processor for high-speed viterbi and trellis coded modulation decoding
US8255780B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 18, 2010 |
| Grant date | Aug 28, 2012 |
| Priority date | — |
| Expiry date | Jan 16, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/256
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An application specific processor to implement a Viterbi decode algorithm for channel decoding functions of received symbols. The Viterbi decode algorithm is at least one of a Bit Serial decode algorithm, and block based decode algorithm. The application specific processor includes a Load-Store, Logical and De-puncturing (LLD) slot that performs a Load-Store function, a Logical function, a De-puncturing function, and a Trace-back Address generation function, a Branch Metric Compute (BMU) slot that performs Radix-2 branch metric computations, Radix-4 branch metric computations, and Squared Euclidean Branch Metric computations, and an Add-Compare-Select (ACS) slot that performs Radix-2 Path metric computations, Radix-4 Path metric computations, best state computations, and a decision bit generation. The LLD slot, the BMU slot and the ACS slot perform in a software pipelined manner to enable high speed Viterbi decoding functions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.