Solver for modeling a multilayered integrated circuit with three-dimensional interconnects
US8255849B1 · kind B1 · utility
7Cited by
5References
25Claims
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Key dates
| Filing date | Apr 14, 2009 |
| Grant date | Aug 28, 2012 |
| Priority date | — |
| Expiry date | Nov 16, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods for modeling a multilayer integrated circuit include three-dimensional interconnect models in multilayered substrates for greater accuracy. Mesh models are used to resolve effects of nearby elements and grid models are used to resolve effects of far-away elements. Sidewall mesh elements of three-dimensional interconnects are projected onto parallel (or substantially parallel) grids between the top and bottom walls of the interconnects so that grid models can be used to resolve three-dimensional effects of interconnects in multilayered substrates.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.