Routing nets over circuit blocks in a hierarchical circuit design
US8255855B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 23, 2009 |
| Grant date | Aug 28, 2012 |
| Priority date | — |
| Expiry date | Jul 12, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/394
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Some embodiments of the present invention provide a system that routes nets over circuit blocks in a hierarchical circuit design. During operation, the system can receive a set of circuit blocks. At least some terminals of the circuit blocks may be desired to be electrically linked together using a net which is expected to be routed over one or more circuit blocks. The system may divide an area associated with a block (e.g., an area in a metal layer which is situated above the block) into a set of tiles. Next, the system may assign costs to at least some of the tiles in the set of tiles. The system can then use the costs during routing. Note that using the costs of the tiles during routing makes it more likely that buffers can be used wherever required to meet slew and timing requirements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.