DC path checking in a hierarchical circuit design
US8255856B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 11, 2008 |
| Grant date | Aug 28, 2012 |
| Priority date | — |
| Expiry date | Aug 4, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/367
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer implemented method is provided for use in evaluating a hierarchical representation of a circuit design encoded in a computer readable medium comprising: traversing a circuit path within a higher level circuit that includes a reference potential connection, to identify a port of a call to a first lower level circuit that is DC path connected to the reference potential; identifying a first DC port group that includes each port of the call to the first lower level circuit that is DC path connected to the identified port of the call to the first lower level circuit; automatically marking as DC path connected to the reference potential, each port of the call to the first lower level circuit that is a member of the first DC port group; and traversing a circuit path within the first lower level circuit to identify a circuit path within the first lower level circuit that is DC path connected to a marked port of the first lower level circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.