Scanning circuit and scanning method for keyboard
US8258985B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | May 17, 2010 |
| Grant date | Sep 4, 2012 |
| Priority date | — |
| Expiry date | Apr 18, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M11/20
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A scanning circuit includes n input ports K1˜Kn arranged in n rows L1˜Ln; and m−2 output ports W2˜(m−1) arranged in m columns P1˜Pm. The n rows and the m columns define a switch matrix including n*m switches. Ends of the switches in the same row are connected to one of the n input ports K1˜Kn, respectively. The ends of the switches in the column P1 are connected to ground. The ends of the switches in the same column of the columns P2˜P(m−1) are connected to a power supply VCC via resistors R2˜R(m−1) and the m−2 output ports W2˜W(m−1), respectively. The ends of the switches in the columns Pm are connected to ground via a resistor Rs and the power supply VCC via the resistors R2˜R(m−1) and diodes D2˜D(m−1), respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.