Multi-level phase-change memory device and method of operating same
US8259490B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 15, 2010 |
| Grant date | Sep 4, 2012 |
| Priority date | — |
| Expiry date | Jan 15, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2013/0092
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-level cell (MLC) phase-change memory device divides data into data groups each comprising multiple bits of data, and stores each of the data groups in a selected phase-change memory cell. A data group is stored in a selected phase-change memory cell by applying a pulse current to the selected phase-change memory cell with a pulse current characteristic corresponding to a data value of the data group. The pulse current characteristic can comprise, for instance, a magnitude, downward slope, or duration of the pulse current. Data is read from a selected phase-change memory cell by sensing a voltage of a bitline connected to the selected phase-change memory cell and comparing the sensed voltage simultaneously with a plurality of reference voltages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.