Semiconductor memory device and method for driving semiconductor memory device
US8259495B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 3, 2011 |
| Grant date | Sep 4, 2012 |
| Priority date | — |
| Expiry date | Aug 3, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/40
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a plurality of memory cell transistors arranged in a matrix; a plurality of word lines commonly coupling the control gates of the plural memory cell transistors present in a identical first direction; a plurality of source lines commonly coupling the sources of the plural memory cell transistors present in the identical first direction; a plurality of bit lines commonly coupling the drains of the plural memory cell transistors present in a identical second direction intersecting the first direction; a first transistor having a drain coupled to the source line; a second transistor having a drain coupled to a source of the first transistor, a gate coupled to the word line and a source grounded; and a control line commonly coupling the gates of the plural first transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.