Interrupt optimization for multiprocessors
US8260996B2 · kind B2 · utility
14Cited by
42References
23Claims
0Family size
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Key dates
| Filing date | Apr 24, 2009 |
| Grant date | Sep 4, 2012 |
| Priority date | — |
| Expiry date | Feb 25, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/5033
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Technologies are described herein for allocating interrupts within a multiprocessor computing system. Information communicated to an interrupt controller module can support allocating interrupt response resources so as to maintain processor affinity for interrupt service routines. This affinity can support caching efficiency by executing a specific interrupt handler on a processor that previously executed that interrupt handler. The caching efficiency may be balanced against the benefits of assigning execution of the interrupt hander to another processor that is currently idle or currently processing a lower priority task.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.