Cyclically interleaved dual BCH, with simultaneous decode and per-codeword maximum likelihood reconciliation
US8261167B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 9, 2010 |
| Grant date | Sep 4, 2012 |
| Priority date | — |
| Expiry date | Mar 8, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/373
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and system are provided for forward error correction. Embodiments of the present disclosure provide a strong FEC algorithm that performs similarly to RS(255,239) when a simple decoder is used, and scales up linearly to a full-scale decoder that outperforms all 7% algorithms currently in G.975.1. The Forward Error Correction code is suitable for use in optical transport networks (OTN) and other applications requiring high decode performance and high code rate. Embodiments of the present disclosure provide an FEC code that is a cyclically interleaved dual BCH, with simultaneous decode and per-codeword maximum likelihood reconciliation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.