Technique for modeling parasitics from layout during circuit design and for parasitic aware circuit design using modes of varying accuracy
US8261228B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 1, 2008 |
| Grant date | Sep 4, 2012 |
| Priority date | — |
| Expiry date | Dec 20, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques are presented for accounting for parasitics in the automated design of integrated circuits. In one set of techniques, model values for parasitic models are received on a schematic environment from a user, the parasitic models are evaluated from the schematic using the received model values, the parasitic models are transferred to a layout environment, and the transferred parasitic models are evaluated on the layout environment. In other techniques, model values are received for parasitic models from a user, the parasitic models are evaluated on the layout environment, and the process then backannotates the parasitic models evaluated on the layout environment and corresponding parameter values to a schematic environment. In yet other techniques, a user is presented with a simulation environment within which the user is provided a choice to select between parasitic simulation modes of varying accuracy, the modes including a mode without parasitics and a plurality of modes including parasitics with a varying degree of accuracy. A selection from among the modes is received from the user and simulation test are performed at the selected degree of accuracy.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.