Nonvolatile memory devices and methods of manufacturing the same
US8264026B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 27, 2010 |
| Grant date | Sep 11, 2012 |
| Priority date | — |
| Expiry date | Dec 5, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
Abstract
Nonvolatile memory devices and related methods of manufacturing the same are provided. A nonvolatile memory device includes a tunneling layer on a substrate, a floating gate on the tunneling layer, an inter-gate dielectric layer structure on the floating gate, and a control gate on the inter-gate dielectric layer structure. The inter-gate dielectric layer structure includes a first silicon oxide layer, a high dielectric layer on the first silicon oxide layer, and a second silicon oxide layer on the high dielectric layer opposite to the first silicon oxide layer The high dielectric layer may include first and second high dielectric layers laminated on each other, and the first high dielectric layer may have a lower density of electron trap sites than the second high dielectric layer and may have a larger energy band gap or conduction band-offset than the second high dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.