Programmable power limiting for power transistor system
US8264211B2 · kind B2 · utility
1Cited by
10References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 21, 2008 |
| Grant date | Sep 11, 2012 |
| Priority date | — |
| Expiry date | May 21, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/6874
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Various systems, methods and apparatuses are provided herein for limiting power dissipation in a switch. As one example, a method for limiting power dissipation is disclosed. The method includes monitoring current through the switch, and based at least in part on detecting that the current is at least as great as a predetermined current limit, regulating the current to the predetermined current limit. The method also includes measuring an amount of power dissipated in the switch while the current is being regulated, and opening the switch when the amount of power has reached a predetermined power limit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.