Delay locked loop and method of driving delay locked loop
US8264260B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 12, 2010 |
| Grant date | Sep 11, 2012 |
| Priority date | — |
| Expiry date | Oct 28, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00071
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Provided are a delay locked loop (DLL) having a pulse width detection circuit and a method of driving the DLL. The DLL includes a pulse width detection circuit and a delay circuit. The pulse width detection circuit receives a reference clock signal, detects a pulse width of the reference clock signal, and outputs the detection result as a pulse width detection result signal. The delay circuit receives and delays the reference clock signal, and outputs the delayed reference clock signal as an output clock signal. The delay circuit receives the pulse width detection result signal from the pulse width detection circuit, and controls a time delay in the reference clock signal in response to the pulse width detection result signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.