Offset-voltage calibration circuit
US8264268B2 · kind B2 · utility
3Cited by
10References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 26, 2010 |
| Grant date | Sep 11, 2012 |
| Priority date | — |
| Expiry date | Dec 14, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/66
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Provided is an offset-voltage calibration circuit. The circuit includes a comparator configured to receive at least two comparison voltages and output a result of a comparison between the comparison voltages, an up/down counter (UDC) configured to output an up-counting or down-counting output signal in response to an output signal of the comparator, and a current digital-to-analog converter (DAC) configured to control the amount of current supplied from a node to which the comparison voltage is applied, in response to the output signal of the UDC and control the magnitude of the comparison voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.