Shared memory multi video channel display apparatus and methods
US8264610B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 17, 2007 |
| Grant date | Sep 11, 2012 |
| Priority date | — |
| Expiry date | Aug 22, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N21/4435
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
The invention includes a system and the associated method for decoding multiple video signals. The video signals may be component video, composite video or s-video signals each having multiple portions using a multimode video decoder. A selection stage may combine the multiple video signals and select some of their video signal portions for processing. The selection stage may time-multiplex some of the video signal portions. An analog to digital conversion stage may be shared by the time-multiplexing of the video signals. A decoder stage may decode the various signal portions and provide decoded output video signals. These feature may reduce the overall cost of the system. Various clock signals may be used to operate various stages of a multimode video decoder. Some of the clock signals may run at different frequencies and others may operate at a different phase.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.