Systems and methods for refreshing a memory module
US8264903B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 5, 2010 |
| Grant date | Sep 11, 2012 |
| Priority date | — |
| Expiry date | Feb 12, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/40611
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory module according to certain aspects has a plurality of memory devices arranged into one or more logical ranks. Each logical rank may correspond to a set of at least two physical ranks. The memory module can include a circuit operatively coupled to the plurality of memory devices and configured to be operatively coupled to a memory controller of a computer system to receive a logical rank refresh command. In response, the circuit can initiate a first refresh operation for one or more first physical ranks and then initiate a second refresh operation for one or more second physical ranks. The memory module can further include a memory location storing a refresh time (tRFC) value accessible by the memory controller and based at least in part on a calculated maximum amount of time for refreshing the logical rank.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.