System and method for low-latency processing of intra-frame video pixel block prediction
US8265152B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 10, 2008 |
| Grant date | Sep 11, 2012 |
| Priority date | — |
| Expiry date | Jun 30, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N19/593
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A method and system for low-latency processing of intra-frame video pixel block prediction including: predicting a pixel block based on boundary pixels of left and upper neighbor blocks of said pixel block; subtracting said predicted pixel block from a source pixel block to generate a prediction error; forward transforming and quantizing said prediction error to generate a residual data; inverse transforming and quantizing said residual data; adding said predicted pixel block to said inverse transformed and quantized residual data to generate a reconstructed pixel block; pre-computing blocks of DC-coefficients used with luma and chroma intra prediction modes; pre-computing mode selection of a best prediction mode of said luma and chroma intra prediction modes; and outputting said residual data to be used in entropy or arithmetic coding, and a reconstructed data used for motion prediction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.