Data processing apparatus that processes incoming bits
US8266346B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 19, 2003 |
| Grant date | Sep 11, 2012 |
| Priority date | — |
| Expiry date | Aug 1, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/06
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A data processing apparatus receives a communication signal that contains temporally successive bits. A programmable processor circuit executes a plurality of series of programmed instructions for operations such as parity checking, each at a time of reception of a respective one of the bits. The processor circuit suspends operation each time after executing a respective one of the series of instructions. A synchronization circuit triggers execution of respective ones of the series, each time at the time of reception of the respective one of the bits, and, except for a last one of the series, prior to reception of one or more later bits that contribute to the data word.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.