Protection against attacks by generation of errors on jump instructions
US8266423B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 18, 2005 |
| Grant date | Sep 11, 2012 |
| Priority date | — |
| Expiry date | Nov 15, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F21/55
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for securing a program against attacks by error, i.e. in a chip card, wherein at least one jump instruction, including a relative address chosen from a plurality of possible relative addresses, is identified in the program, wherein the at least one jump instruction makes it possible to reach a targeted address inside the memory area extending before and after the jump instruction and regrouping the plurality of possible relative addresses, inside the memory area, wherein an instruction to be preserved is identified and, in order to secure at least the instruction, at least one first non-operative batch including at least one instruction is inserted, the insertion being carried out in such a way as to ensure that the insertion is compatible with maintenance of the address targeted by the jump instruction inside the memory area and that the insertion is compatible with the normal running of the program.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.