Bus with error correction circuitry
US8266494B2 · kind B2 · utility
0Cited by
8References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 17, 2008 |
| Grant date | Sep 11, 2012 |
| Priority date | — |
| Expiry date | Jul 13, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2001/0094
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A data bus including a plurality of logic blocks coupled in series, each logic block including at least one buffer for buffering at least one data bit transmitted via the data bus and at least one of the logic blocks further including circuitry coupled in parallel with the at least one buffer and arranged to determine a first bit of error correction code associated with the at least one data bit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.