Transparent transistor with multi-layered structures and method of manufacturing the same
US8269220B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 4, 2009 |
| Grant date | Sep 18, 2012 |
| Priority date | — |
| Expiry date | Sep 25, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/62
Abstract
Provided is a transparent transistor including a substrate, source and drain electrodes formed on the substrate, each having a multi-layered structure of a lower transparent layer, a metal layer and an upper transparent layer, a channel formed between the source and drain electrodes, and a gate electrode aligned with the channel. Here, the lower transparent layer or the upper transparent layer is formed of a transparent semiconductor layer, which is the same as the channel. Thus, the use of the multi-layered transparent conductive layer can ensure transparency and conductivity, overcome a problem of contact resistance between the source and drain electrodes and a semiconductor, and improve processibility by patterning the multi-layered transparent conductive layer all at once, while deposition is performed layer by layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.