Timing skew error correction apparatus and methods
US8269528B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 18, 2010 |
| Grant date | Sep 18, 2012 |
| Priority date | — |
| Expiry date | Mar 17, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/1245
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Apparatus and methods disclosed herein operate to compensate for skew between inverse phases (e.g., differential phases) of an analog signal appearing at the inputs of an analog signal capture circuit such as a track-and-hold or sample-and-hold circuit associated with an ADC or similar device. Each of two capture clocks is used to capture one of the inverse phases. One or more delay circuits are configured to create a differential delay between clock transitions associated with the two capture clocks. The differential delay is proportional to the input skew between the inverse phases. The phases are consequently sampled at substantially identical points on a phase domain axis. Embodiments operate to create phase sampling synchronicity and to thereby decrease the amplitude of a common-mode signal component that results from the skew. Increased linearity and decreased distortion may result.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.