Power-supply noise suppression using a frequency-locked loop
US8269544B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 1, 2010 |
| Grant date | Sep 18, 2012 |
| Priority date | — |
| Expiry date | Mar 25, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/18
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated circuit that includes a digitally controlled oscillator (DCO) that adjusts a clock frequency of a critical path of the integrated circuit based on the variations in a power-supply voltage of the DCO and the critical path is described. This DCO may be included in a feedback control loop that includes a frequency-locked loop (FLL), and which determines an average clock frequency of the critical path based on a reference frequency. Furthermore, the DCO may have a selectable delay characteristic that specifies a delay sensitivity of the DCO as a function of the power-supply voltage, thereby approximately matching a manufactured delay characteristic of the critical path. Additionally, for variations in the power-supply voltage having frequencies greater than a resonance frequency associated with a chip package of the integrated circuit, adjustments of the clock frequency may be proportional to the variations in the power-supply voltage and the selectable delay characteristic.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.