Dithering a digitally-controlled oscillator output in a phase-locked loop
US8269563B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 10, 2008 |
| Grant date | Sep 18, 2012 |
| Priority date | — |
| Expiry date | Jun 10, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B1/69
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A digitally-controlled oscillator (DCO) of a PLL is dithered such that a DCO_OUT signal has a frequency that changes at dithered intervals. In one example, the DCO receives an undithered stream of incoming digital tuning words, and receives a dithered reference clock signal REFD, and outputs the DCO_OUT signal such that its frequency changes occur at dithered intervals. Where the PLL is employed in the local oscillator of a cellular telephone transmitter, the novel dithering of the DCO spreads digital image noise out in frequency such that less digital image noise is present at a particular frequency offset from the main local oscillator frequency. Spreading digital image noise out in frequency allows a noise specification to be met without having to increase the frequency of the PLL reference clock. By avoiding increasing the frequency of the reference clock to meet the noise specification, increases in power consumption are avoided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.