Circuit arrangement comprising a memory cell field and method for operation thereof
US8270192B2 · kind B2 · utility
0Cited by
6References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 14, 2007 |
| Grant date | Sep 18, 2012 |
| Priority date | — |
| Expiry date | Jan 18, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C17/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit arrangement comprises a memory cell array (2) with at least one memory circuit (99). The memory circuit (99) comprises one non-volatile memory cell (98) inserted in a first current path (106) between a supply voltage terminal (9) and a reference potential terminal (8), and a volatile memory cell (97) inserted in a second current path (107) between the supply voltage terminal (9) and the reference potential terminal (8). The volatile memory cell (97) is coupled to the non-volatile memory cell (98) for reading the non-volatile memory cell (98).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.