Semiconductor memory device and methods of performing a stress test on the semiconductor memory device
US8270239B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 9, 2008 |
| Grant date | Sep 18, 2012 |
| Priority date | — |
| Expiry date | Dec 18, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1204
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device and method of performing a stress test on a semiconductor memory device are provided. In an example, the semiconductor memory device includes a multiplexer arrangement configured to switch a timing signal that controls an internal timing of the semiconductor memory device from an internal signal to an external signal during a stress mode, and further includes one or more word lines of the semiconductor memory device receiving a stress voltage during the stress mode, a duration of the stress mode based upon the external signal. In another example, the semiconductor memory device includes one or more word lines configured to receive a stress voltage during a stress mode, and a precharge circuit configured to provide a precharge voltage to a bit line of the semiconductor memory device during the stress mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.