System and method for parallel interference cancellation with covariance root processing
US8270453B2 · kind B2 · utility
2Cited by
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21Claims
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Key dates
| Filing date | Nov 3, 2008 |
| Grant date | Sep 18, 2012 |
| Priority date | — |
| Expiry date | Jul 9, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B1/7105
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A parallel interference cancellation (PIC) receiver incrementally removes interference from signals in parallel modules in successive stages. For each desired signal, as interfering signals are removed, corresponding updates to a data covariance matrix are modeled as computationally tractable rank-one updates to a root matrix of the covariance matrix. Processing of signals and/or covariance information may be initiated, continued, and/or halted at various stages, e.g., in response to signal or data quality. The PIC receiver using root matrix updates is applicable to a variety of demodulation techniques.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.